Digital System 2 + Lab (N EE-2019 CONTROL SYSTEMS)
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Lecture 1: FSM and Timing Analysis
Lecture 0_ Course Introduction
Lecture 1_ FSMs and Timing Analysis of Sequential Circuit
Class Recording Week 1
Lecture 2: FSM and Timing Analysis (Cont.)
DS II Quiz I: Finite State Machines
Supplementary File: Understanding Timing Diagram
Supplementary Material: Understanding Setup Time, Hold Time, etc.
DS II Homework 1
Lecture 3: Intro to VHDL
Quiz 2: Timing Constraint of Sequential Circuit
Introduction to VHDL: Basics
Introduction to VHDL Part II
Introduction to VHDL (cont.)
Homework II: Entitiy and Architecture in VHDL
VHDL Part III
Quiz 3
Concurrent Signal Assignment and Registers
CSA and Registers
MID EXAM
Mid Exam
CSA, Registers, and Clocked Process
CSA, Registers, and Clocked Process
Homework III
Finite State Machine in VHDL
Quiz 4
Finite State Machine in VHDL (Continued)
FSM in VHDL
Homework IV
Register Transfer Level Design
Quiz 5
Lecture 4_RTL Design
RTL Design (Cont'd)
Homework 5
Data-dominated RTL Design
Quiz 5
Homework 6
FINAL EXAM
Final Exam
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44491_Digital System 2 + Lab
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Digital System 2 + Lab (N EE-2019 CONTROL SYSTEMS)
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20212
Night (20212)
Electrical Engineering (20212/N)
44491_Digital System 2 + Lab
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Digital System 2 + Lab (N EE-2019 CONTROL SYSTEMS)
Teacher:
Iksan Bukhori
Skill Level
:
Beginner
Self enrolment (Student)
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